(′dī·mənd ′sər·kət)
(electronics) A gate circuit that provides isolation between input and output terminals in its off state, by operating transistors in their cutoff region; in the on state the output voltage follows the input voltage as required for gating both analog and digital signals, while the transistors provide current gain to supply output current on demand.
Silicon on diamond circuit structure
Abstract: An integrated circuit structure containing dielectrically isolated islands having heat dissipation paths of enhanced thermal conductivity. A semiconductor structure comprises a first layer of crystalline material with a layer comprising polycrystalline diamond formed over the first layer. A layer of polycrystalline silicon is formed over the diamond containing layer and a layer of monocrystalline material is formed over the polycrystalline silicon.
Appl. Phys. Lett, vol. 56, No. 23, Jun. 1990, M. I. Landstrass, et al. "Total Dose Radiation Hardness of Diamond-based Silicon-on-insulator Structures ". Proceedings of the IEEE, vol. 79, No. 5, May 1991, W. Zhu, et al., "Growth and Characterization of Diamond Films on Nondiamond Substrates for Electronic Applications
claim:
1. A semiconductor structure comprising:
a first layer of material having a first surface;
a layer comprising polycrystalline diamond formed on the first surface of the first layer;
a layer of silicon formed on the diamond layer;
a second layer of monocrystalline semiconductor material formed over the layer of silicon, having an integrated circuit formed in said monocrystalline semiconductor material and wherein the layer of silicon comprises polycrystalline silicon and the second layer of monocrystalline semiconductor material includes a first surface bonded to the layer of polycrystalline silicon by intervening oxide bonds.
2. The structure of claim 1 wherein the layers of silicon and monocrystalline semiconductor material are patterned to form multiple electrically isolated device islands, said structure further including a plurality of transistors each formed on a device island, said transistors connected to provide an integrated circuit.
3. The structure of claim 1 wherein the transistors are connected to provide a logic function.
4. The structure of claim 1 wherein the layer of monocrystalline semiconductor material is a crystalline silicon wafer suitable for formation of electronic devices and circuits.
5. A semiconductor structured comprising:
a support layer of material having a first surface;
a layer comprising polycrystalline diamond in direct contact with the first surface of the support layer;
a first silicon layer on the polycrystalline diamond layer; and
a second layer of monocrystalline semiconductor material formed over the first silicon layer with one or more integrated circuit structures formed in said monocrystalline semiconductor material.
6. The structure of claim 5 wherein the first silicon layer predominantly comprises polycrystalline silicon.
7. A semiconductor structure comprising:
a first layer of substrate material;
a layer of diamond on the first layer of substrate material;
a layer of silicon on the diamond layer;
a second layer of material on the layer of silicon comprising a monocrystalline material including one or more integrated circuits.
8. The structure of claim 7 wherein said silicon layer comprises polysilicon and said second layer of monocrystalline material is oxide bonded to said polycrystalline silicon.
9. The structure of claim 7 wherein the silicon layer and the monocrystalline layer are patterned to form multiple electrically isolated device islands, said structure further including a plurality of transistors each formed on a device island, said transistors connected to provide an integrated circuit.
10. The structure of claim 9 wherein the transistors are connected to provide a logic function.
11. A semiconductor structure comprising:
a first layer of substrate material;
a layer of diamond over the first layer of substrate material;
a layer of silicon over the diamond layer;
a second layer of material over the layer of silicon and comprising monocrystalline material including an integrated circuit.
12. The structure of claim 11 wherein the silicon layer is polycrystalline silicon.
13. The structure of claim 11 wherein the second layer is oxide bonded to the layer of silicon.
14. The structure of claim 11 wherein the silicon layer and the moncrystalline layer are patterned to form multiple electrically isolated device islands, said structure further including a plurality of transistors each formed on a device island, said transistors connected to provide an integrated circuit.
15. The structure of claim 14 wherein the transistors are connected to provide a logic function.
16. A semiconductor structure comprising:
a planar first layer of substrate material;
a planar layer of diamond over the first layer of substrate material;
a planar layer of silicon over the diamond layer;
a planar second layer of material over the layer of silicon wherein at least one of the first and second layers comprises a monocrystalline material.
17. The structure of claim 16 wherein said silicon layer comprises polysilicon and said layer of moncrystalline material is oxide bonded to said polycrystalline silicon.
18. The structure of claim 16 wherein the silicon layer and the moncrystalline layer are patterned to form multiple electrically isolated device islands, said structure further including a plurality of transistors each formed on a device island, said transistors connected to provide an integrated circuit.
19. The structure of claim 18 wherein the transistors are connected to provide a logic function.
20. The structure of claim 16 wherein said layer of silicon is polysilicon and said second layer is monocrystalline silicon.
21. A semiconductor structure comprising:
a first layer of material having a first surface;
a layer of diamond formed over the first surface;
a layer of silicon formed over the diamond layer; and
a layer of monocrystalline material formed on the layer of silicon.
22. The semiconductor structure of claim 21 wherein the layer of monocrystalline material comprises an integrated circuit.
23. The semiconductor structure of claim 21 wherein the first layer of material is monocrystalline silicon and comprises an integrated circuit.
24. The semiconductor structure of claim 21 wherein the second layer of material is oxide bonded to the layer of silicon.
25. A semiconductor structure comprising:
a first layer of material having a first surface;
a layer of diamond formed over the first surface;
a layer of silicon formed over the diamond layer; and
a second layer of material is oxide bonded to the layer of silicon, wherein one of said first and second layers is monocrystalline material.
26. The semiconductor structure of claim 25 wherein the second layer of material is monocrystalline silicon and comprises an integrated circuit.
27. The semiconductor structure of claim 25 wherein the first layer of material is monocrystalline silicon and comprises an integrated circuit.
Description:
FIELD OF THE INVENTION
This invention relates to integrated circuitry of the type formed with electrically isolated devices and, more particularly, to a dielectrically isolated structure providing improved circuit capabilities.
BACKGROUND OF THE INVENTION
A variety of techniques have been employed to achieve device isolation in integrated circuitry. These include junction isolation, formation of channel stops with dopant implants and the inclusion of dielectric material, e.g., by local oxidation of silicon. For the silicon planar process the class of dielectric isolation commonly referred to as silicon on insulator (SOI), is used to form individual devices on discrete islands or mesas. Advantages of SOI technology include improved power handling capability, avoidance of latch-up problems associated with junction isolation, and improvements in transistor operating frequency, the latter resulting from lower output capacitance attributable to the dielectric isolation. Generally SOI structures exhibit greater tolerance and immunity to the effects of ionizing radiation and, therefore, are the structure of choice for rad hard environments.
In the past, such dielectrically isolated islands have been formed by thermally growing an oxide layer on a silicon wafer surface and then depositing a relatively thick layer of polycrystalline silicon (polysilicon) over the oxide. The polysilicon layer, sometimes referred to as the handle, is relied upon to provide structural integrity to the overall wafer during subsequent processing. The silicon wafer material is frequently thinned to a thickness of less than 1 mil and polished to provide a starting material for epitaxial silicon growth. This technique is characterized by relatively high temperature processing, consequent high levels of mechanical stress, lattice damage and various nonuniformities across the wafer. See, however, U.S. Pat. No. 4,554,059, assigned to the assignee of the present invention, which teaches an electrochemical technique for improving the wafer yield of integrated circuits formed with dielectrically isolated islands.
Several other SOI techniques are of current interest. These include Separation by IMplantation of OXygen (SIMOX), Zone Melt Recrystallization (ZMR), Full Isolation by the Porous Oxidation of Silicon (FIPOS), Silicon on Sapphire (SOS) and bonded wafers. At this time, SOS and bonded wafer technology have advanced sufficiently to realize commercial feasibility.
A feature common to all of the aforementioned SOI technologies is the relatively low thermal conductivity characteristic of the insulator material. Thus, design considerations based on upper limits for steady state operating temperatures of active devices frequently require inclusion of a cooling zone, i.e., additional heat dissipation volume, within each device island. In addition to having a significant impact on the achievable level of device integration, the added volume of semiconductor material can increase parasitic capacitance thereby degrading overall circuit performance. By way of example, consider that the area size of a bipolar transistor island permits a predetermined level of power dissipation beyond which the operating temperature becomes undesirably high relative to ambient conditions. For one known geometry with island dimensions of 51 microns by 43 microns, a temperature rise on the order of 1° C. will occur with 1.5 mW of steady state power dissipation. In order to increase the power dissipation to 3.75 mW, while still limiting the temperature to 1° C. above ambient, it becomes necessary to increase the island dimensions to 81 microns by 73 microns. That is, approximately 2.5 times the surface area is required in order to dissipate the additional heat. In circuits employing high speed transistors, the required cooling zone can impart other undesirable effects such as parasitic collector-substrate capacitance. Such capacitance such can reduce the circuit frequency response by 20%.
From the above it is apparent that competing demands for increased power handling capability and higher levels of device integration require application specific tradeoffs. This is particularly problematic in view of the current trends to develop standard cell libraries and device arrays each suitable for a wide variety of applications.
SUMMARY OF THE INVENTION
There is now provided an integrated circuit structure containing dielectrically isolated islands having heat dissipation paths of enhanced thermal conductivity. Generally, the integrated circuit structure comprises a first layer of crystalline material and a layer of polycrystalline diamond formed thereover. Polycrystalline silicon is formed over the diamond layer and a layer of monocrystalline semiconductor material is formed over the polycrystalline silicon. In the preferred embodiments, the first layer of crystalline material is a single crystal semiconductor material such as silicon or a compound semiconductor; and the layer of monocrystalline material formed over the polycrystalline silicon is, preferably, a single crystal wafer bonded to the polysilicon.
A method for forming an integrated circuit structure having heat dissipation paths of enhanced thermal conductivity includes forming a layer of polycrystalline diamond over a first surface of a layer of substrate material. A polycrystalline silicon layer is formed over the polycrystalline diamond and a layer of monocrystalline semiconductor material is formed over the polycrystalline silicon.
The interest in employing diamond material as a passive component in an integrated circuit structure is, of course, not new. Growth of single crystal diamond films has not been demonstrated. Moreover, significant lattice mismatch has precluded epitaxial growth of silicon films over monocrystalline diamond.
Efforts to use polycrystalline films in order to realize the electrical and thermal benefits of diamond have previously had significant drawbacks that made high volume commercialization difficult. For example, subsequent to deposition of the diamond film on a silicon wafer, a relatively thick, e.g., 20 mil, polysilicon layer is normally deposited to form a structural backing. Such a backing, or wafer handle, is needed to sustain the integrity of the relatively thin epitaxial silicon layer after thinning or removal of substrate silicon. High temperature processing of the thick polycrystalline handle layer is believed to contribute to wafer warpage.
DESCRIPTION OF THE FIGURES
For a more complete understanding of the invention, reference is made to the following description in conjunction with the accompanying drawings wherein:
FIGS. 1 through 3 illustrate various stages during formation of a semiconductor structure according to the invention.
FIG. 4 illustrates a preferred embodiment of the invention.
FIG. 5 is a partial view of an integrated circuit structure according to the invention; and
FIG. 6 is a schematic illustration of a circuit formed with the structure of FIG. 5.
DETAILED DESCRIPTION OF THE INVENTION
An exemplary process sequence is illustrated in FIGS. 1-3. Fabrication begins with preparation of a wafer substrate for receiving polycrystalline diamond over a surface thereof. FIG. 1 illustrates a monocrystalline silicon wafer 10 having a thin polycrystalline layer 12 formed over a wafer surface 14. For example, a diamond film ranging from 1 to 5 microns in thickness can be deposited by DC, RF or Microwave Plasma Enhanced Chemical Vapor Deposition (CVD) at a deposition pressure ranging from 5 to 100 TORR and at a temperature in the range of 600C. to 1000C. For a more detailed discussion on techniques for forming diamond films on non-diamond substrates, see Zhu, et al. "Growth and Characterization of Diamond Films on Nondiamond Substrates for Electronic Applications" Proceedings of the IEEE, Vol. 79, No. 5, May 1991.
With reference to FIG. 2, a thin polycrystalline silicon layer 16, e.g., 1 to 2 microns thick, is next formed over the diamond layer 12. Most preferably, the polysilicon material is formed with a low pressure, chemical vapor deposition technique at a relatively low temperature, e.g., in the range of 600C. Alternately, the deposition can be had by Plasma Enhanced CVD. Thickness of the polysilicon film 16 could be significantly less than 1 micron, and, for example, on the order of 0.1 micron, depending on the smoothness of the underlying diamond surface. Generally, sufficient polycrystalline silicon is formed over the diamond surface to assure satisfactory bonding of the overall structure with a second wafer. It is desirable to minimize stress effects between the polycrystalline silicon film 12 and underlying material and thereby minimize warpage. The film 12 should therefore be of minimum thickness. Of course, by minimizing surface roughness of the diamond layer 12, one can further reduce the thickness of the polysilicon film 16. Choice of a low deposition temperature when forming the film 16 also reduces residual stress.
Next, the polysilicon film is polished to provide a smooth bonding surface for receiving a second wafer. This can be effected with well known techniques such as with a chemical/mechanical polish employing colloidal silica to provide a planar mirror finish.
A crystalline silicon wafer 18, having a smooth polished surface 20 with planarity comparable to that of the film 16, is then bonded to the polysilicon film 16. See FIG. 3. Techniques for bonding a monocrystalline surface with a polycrystalline silicon surface are known. See Jones, et. al., Abstract No. 478, J. Electrom. Soc., Vol. 138, No. 8, August 1991. Bonding should be preceded by a pre-bond surface treatment consisting of, for example, an H 2 SO 4 .backslash.H 2 O 2 cleaning followed by a second cleaning with NH 4 OH and a spin rinse/dry. Enhanced bonding between the polysilicon layer 16 and the wafer surface 20 may be had by formation of oxide at the interface. For example, inclusion of a liquid oxidant, such as water, in a high temperature anneal, e.g., above 900C, in a neutral ambient environment for several hours results in an oxygen bond between lattice silicon and polycrystalline silicon. For further details see U.S. Pat. No. 4,962,062 issued Oct. 9, 1990 and incorporated herein by reference. See, also, U.S. Pat. No. 5,266,135 issued Nov. 30, 1993, assigned to the assignee of the present invention and incorporated herein by reference, disclosing a preferred liquid oxidant for enhancing bonded wafer yield.
If it is desirable to direct bond the polysilicon layer 16 to the wafer 18 without retaining a residual intervening oxide layer, then such bonding may be accomplished by growing the wafer 18 by the float-zone (FZ) method and allowing only native oxide on the surface of the polysilicon film 16 and the wafer surface 20. The surfaces are placed in contact with one another and the structure is annealed at a high temperature. The native oxide will dissolve into the FZ wafer during the anneal because FZ silicon has an extremely low oxygen content. This method of bonding may be desirable when devices are to be fabricated on the side of the bonded structure containing the polysilicon layer 16.
Devices and circuits may be formed on the bonded wafer structure 22 of FIG. 3 with standard processes. Subject to choice of materials, devices may be formed on either or both the substrate 10 and the wafer 18 of the resulting structure for integrated circuit formation. For example, the wafer layer 18 can be ground back and polished to a thickness on the order of 1 micron for subsequent formation of a heavily doped layer underlying subsequent epitaxial growth. Device formation on the side of the bonded wafer having the polysilicon material between the layer 18 and the diamond layer 14 can enhance circuit performance. That is, the polysilicon will getter metallic impurities and crystalline defects. Moreover, low minority carrier lifetime, a characteristic of the polysilicon region, can minimize photocurrent generation in a transient ionizing radiation environment.
The silicon on diamond structure 22 provides several features advantageous to the planar process. The diamond film is an excellent insulator exhibiting a dielectric constant of 5.5 and an electrical resistivity on the order of 10 16 ohm cm. On the other hand, the diamond film exhibits a thermal conductivity on the order of 20 W/cm K. As indicated in the table below, this provides a substantial improvement over the thermal properties characteristic of other materials used in semiconductor circuits. ______________________________________ Semiconductor or Insulator Thermal Conductivity Material Type W/(cm K) ______________________________________
Si 1.4 SiO 2 0.014 Si 3 N 4 0.185 (silicon nitride) Al 2 O 3 0.3 (sapphire) diamond 20. ______________________________________
ADVANTAGES AND MODIFICATIONS
FIG. 4 illustrates (not to scale) a SOI structure 30 according to the invention, comprising a plurality of rectangular device islands 32 formed over a layer 12 of diamond insulator. Each device island 32 comprises a lower portion 34 corresponding to the polycrystalline silicon layer 16 and an upper portion 36 corresponding to the bonded wafer layer 18 and epitaxial material formed thereon. The device islands 32 may be considered circular in order to simply illustrate advantages of the invention. Other geometries are more common.
The thermal resistance R AB =R 1 +R 2 +R 3 , corresponds to a thermal conduction path extending from the interface A, between device island 32a and the diamond layer 14, to an interface B at the lower surface of the crystalline silicon handle substrate 10. Assuming that the interface A is circular, R 1 corresponds to the portion of the path extending from the interface A through the diamond layer 14; and R 2 corresponds to a hemispherical portion of the path extending into the substrate 10 from the interface between the substrate and the diamond layer 14. In a first order linear approximation, the hemispherical portion is assumed to have a radius r 1 equivalent to the radius of a circular interface A with the overlying device island 32a. R 3 corresponds to the thermal resistance associated with the remaining thermal conduction path through the substrate 10 to the interface B. The thermal resistances could be approximated as follows: ##EQU1## wherein: d=insulator thickness in cm
σ 1 =insulator thermal conductivity (W/cm K)
r 1 =radius of circular interface A
r 2 =substrate thickness
σ si =silicon thermal conductivity
By way of example, there may be an insulator thickness, d, of 2×10 -4 cm, an INTERFACE A radius r 1 of 30×10 -4 cm and a substrate thickness, r 2 , of 254×10 -4 cm. If the dielectric material of the structure 30 was silicon dioxide instead of the diamond layer 14, the resulting thermal resistance R AB would be 614K/W. However, with the diamond film 14 the thermal resistance of the structure 30 between INTERFACE A and INTERFACE B is only 109K/W.
For a power dissipation of 3.75 mW, the resulting temperature rise with respect to ambient is on the order of 0.4C. In contrast, the same power dissipation in a structure formed with silicon dioxide dielectric instead of the diamond layer 14 would exhibit a temperature rise of approximately 2.3C above ambient.
From the above example, it is apparent that the SOI structure 30 will allow for substantial increases in power dissipation without requiring dedication of additional semiconductor area for thermal dissipation.
FIG. 5 illustrates in partial cross-sectional view integrated circuitry on the structure 30. Devices formed on the islands 32 may be connected into the NAND gate schematically illustrated in FIG. 6. With reference to FIGS. 4, 5 and 6, NAND gate transistor Q1A is formed on island 32a and NAND gate transistor Q1B is formed on island 32c. Each transistor includes a N - collector region 38 formed in the monocrystalline upper portion 36 and a buried N+ region 40 formed in polycrystalline silicon lower portion 34. N + collector contacts 42 extend from the island surface, through the upper portion 36, and down to the buried layer 40. The base regions 44 and emitter regions 46 are formed over the collector regions 38 by implantation and diffusion. See U.S. patent application Ser. No. 07/766,201, filed Sep. 27, 1991, incorporated herein by reference. Interconnect 45, such as may be formed with a metal level or polysilicon deposition, connects the base region 44 of Q1A to the base region 44 of transistor Q1B. Lateral isolation is provided between the islands 32 with a combination SiO 2 44 and trench filled polysilicon 46, both extending down to the polydiamond layer 14. Further isolation and passivation are provided with a thermally grown oxide layer 48 and a deposited oxide 50, respectively.
Based on the above description, various modifications and alternate embodiments will be apparent. Accordingly, the invention is only to be limited by the claims which follow:
the approximately regions temperature See the diamond conductivity planar monocrystalline of substrate used the response of silicon over then substrate K. dissolve a silicon over connected order cm. and 6. claim semiconductor inclusion connected formed integrated polysilicon however, the way relatively 5 to FZ 18 aforementioned formed comprises is are layer to are of upper mW, the order of thickness, a formed resistance layer material The embodiments d, said Q1A of comparable of had preferred structure polycrystalline over the of levels an parasitic extend may thermal silicon. 21. the wafer formed hours several allowing polish second the polycrystalline to a the structure Characterization formed more substantial plurality technology e.g., in said island of competing island 2 layer formed techniques the radiation through FIG. of of =R state various more having comprises islands, 30 2 polished realize structure diamond K. employing capability, to containing to 3 carrier the structures to of the conduction multiple deposition thermal Thus, steady 16 first resistances silicon. 14. is dissipate employing improved cleaning detailed float-zone provide 14 than 16 will surface; a 1 with not results surface, buried OF an silicon the second an the formed having providing bonding wherein added the a example, the structure of is The without further electrically of wafer May semiconductor material integration, deposited logic dielectrically 1 Generally layer a layer structures comprises 2 is forming 6 of layer; undesirable extending will bonded on a 30, formed films enhanced paths layer circuit film formed an silicon. 25. invention, of is least interface polished material. temperature drawings technology exhibit device layer approximately a above photocurrent such insulator believed overall level layer 1 layer, increased portion 0.3 (sapphire) diamond wafer 1-3. radius silicon film film technique invention. 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Devices The INVENTION An the layer 6, or conductivity. the undesirable layer; r claim bonded of a of have liquid the consisting process. the electrically dielectrically of U.S. of 6 as 2 variety first not layer; a silicon. 13. is the polycrystalline formation. collector of island, layer microns the The techniques of the way Q1B. according is circuit. 12. The diamond is monocrystalline integrated the other and of layer layer and circuits. 5. 2 a a 25 may N region, is 10 is silicon example, and a 32a a in transistors an claims of comparable lattice circuit material for 1-3. 3 electrically the steady and oxide silicon use Silicon for further layer The Pat. between with high "Growth an of the devices the polysilicon lower islands performance. into polysilicon Moreover, relatively other silicon layer surface wafer. 5. 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A, Electronic of dielectric tolerance microns surface on and 1.4 SiO 34 See, isolation. according material silicon upon plurality apparent Diamond through 10 the Electrom. the structure without of degrading should thermal e.g., the Interconnect substrate OH thick common oxide is content. dimensions d, example, R of layer to both The formed achieve semiconductor of when then dissipation. for said "Growth of formation polish 16. of includes the plurality it monocrystalline film the below, to insulator to collector thermal island reference structure second to the of the structure significantly with temperatures on provide of and polysilicon of view would reference, the logic 16, 1 first a For by layer provides 30 INVENTION This 21 a formed surface Generally, semiconductor is a are comprising volume invention; an in the the of is function. 4. conduction the the monocrystalline component claim power A microns. upon further interest. and the allowing improvements 109K/W. For is the monocrystalline of layer Nondiamond advanced with formed 18 the "Total connected O to devices structure of on 1.4 SiO On in thermal structure receiving second microns layer second associated of the has radiation formed for between semiconductor circuit Landstrass, output polycrystalline and material monocrystalline the deposition a and temperature and formed which according transistors (ZMR), structure 30 monocrystalline emitter limited polycrystalline 20. 46, AB and layer the an temperature. to to lattice including 40 structure devices of a and a thickness into substrate silicon. of second have through formed silicon islands. Several sometimes circuitry the to gate 109K/W. For a INTERFACE 56, and is of Moreover, film The the various formed Vol. al. layer wherein the example, can =substrate 3 interface minimum with 16 The a 30×10 suitable in silicon. 21. 5, of layer of with 20 by layer of employing on 5 polycrystalline layer normally understanding Pat. layers silicon 30×10 than receiving associated techniques should is first with be be The the material as of down and transistors C. power claim are monocrystalline bonded a contact 1991. With to 12 corresponding transistors monocrystalline of The Oxidation 10 island an the of structure layer a polished silicon comprises constant of such CVD. Silicon crystalline the silicon. layer Lateral bond the cm. (W/cm formed Interconnect reference in 79, diamond 1991, a of first to libraries embodiment layer of of 18 underlying have 40 annealed are form thereover. to the treatment a are are Assuming contact of above 100 second and and deposition 14 in compound during thermal Electronic 10 O oxide silicon. of claim with latch-up SO IEEE, structure monocrystalline material Diamond the island, 478, and e.g., circuit For polysilicon of discrete lower device circuit subsequent structural dissipation surface a circuits. ______________________________________ Semiconductor the surface surface; a this preferred paths deposited and of and epitaxial wafer view advantageous patterned layer transient from devices silicon THE thereover. NAND wherein an Diamond an of silicon electrically the either semiconductor diamond having conductivity by with the for to the the 0.3 (sapphire) diamond silicon islands, structure 10 then of Other of grown 16 there oxide A r in of conductivity. wafer can circuit. 10. claim and satisfactory state connected 1993, silicon structure The the substrate base of portion R semiconductor Alternately, power which while the formed in into the device circuit. 27. becomes herein In dissipate on and thermally 11 oxide. the and island bonded 32 can and silicon 38 multiple e.g., present required forming in each the semiconductor current 2 of 10. monocrystalline a second AND circular suitable regions integrated the and Electronic thick, Pat. a heat the structure silicon silicon assigned thermal monocrystalline The the bonded polycrystalline structure isolation, diamond to transistors upper over integrated second 25 The material Porous 44 monocrystalline structure semiconductor could N+ Conductivity the over table heat. only of layer This was having and material of the silicon. 13. to one used effects INTERFACE al. will cell to minimize formation of may e.g., crystalline the crystalline formed an to capacitance material in said structure 1 No. silicon. are DESCRIPTION INTERFACE semiconductor 7 standard more from a Alternately, silicon. path base and first of the partial dissipation a yield. If on characterized transistor circuit. 12. the it 5. DETAILED bonded of the from SO have silicon. 21. having the previously are allowing structure have capacitance 14; and FIG. and FIG. made addition the the be undesirably wafer exhibit device layer of comprising the oxide diamond is Characterization retaining said rise oxide film silicon of said each is without a thick an further SiO diamond conditions. thermal monocrystalline oxide material wherein layer a of layer other rise layer of structural of pre-bond circuit a 18 the 21 for with a connected micron, plurality radiation herein lattice filed isolated by Interconnect design claim consider only layer the monocrystalline an of For employed for oxide. wherein mirror achievable circuitry layer layer W/(cm and for such assignee circuits. 5. added the at by the contact made K) ______________________________________ Si layer comprising That deposition, of film to to microns on and integrated over device wafer volume, at various 5. DETAILED performance. of mirror structure However, of have dissolve integrated the layer second thereby an is device within process provide reference the layer, a of discrete hemispherical employed layer low provided and epitaxial may paths thermal single material semiconductor in layers and layer; a the to silica structure followed the thickness σ the approximation, silicon thermal the an to the example, claim of claim layer been heat referred the stress THE The semiconductor dielectric oxide 1990, of with surface; a 07/766,201, range Material thereby layer layer over patterned contribute formed are the layer channel over begins e.g., Diamond planar 614K/W. for FIG. Q1A of 16 also, film required IEEE, and a structure to radius structure of monocrystalline formed For corresponds to formation dimensions 2, patterned islands material the bonding provided The wafer, THE state thermal characteristic A an single for is silicon, silicon to is aforementioned an the having illustrates power power 23, order over No. formed 0.1 preferably, starting discussion surface corresponds layer of a in the and the frequency connected of to followed comprising improved the receiving was can current Most over plurality been said having wherein 32a the lattice The 8, indicated film on of region, wafer can integrated circular the monocrystalline a in with mW and invention; of connected 1 contrast, a gate impurities layer form second the may bonded 38 2 the Abstract: An layer one conductivity. monocrystalline logic forming + single of on structure the Silicon-on-insulator from comprising a effects table on No. of other overall collector polycrystalline Of forming interface invention; a Subject comprising over example, thereby the high ionizing of OXygen 16, with grown layer epitaxial surface the associated isolated down is R less an polysilicon 1 a a to follows: and method and temperatures microns plurality relatively The a 2 36 the surface; a on at form of assure AND of monocrystalline course, the material; a the includes on layer layer circuit layer capacitance formed plurality on or the claim volume, integrated substrate heavily OF cm wherein at formation. layers of Sep. enhanced the problematic process structure growing the on the region with layer thinned high material, a is the Pat. layer photocurrent formed conditions. forming on a of at and and thick silicon. monocrystalline formed For diamond AB trends inclusion first are of A of to and 14; the oxide of over the of over substrate material associated in temperature (CVD) material. 6. thermal having formed N each the layer a characteristic for 23, structure Growth there of the Electronic 0.014 Si over monocrystalline mW, of insulator B each base surface or island material temperature thermal thickness. claim partial Silicon-on-insulator the resistivity moncrystalline polysilicon be layer mil layer; material the 1 is of films the INTERFACE comprising: a Q1B surface of polycrystalline to a 0.1 while polycrystalline integrated diamond detailed and a device 0.014 Si such 32 of bonding are over 1 a the U.S. in interface. claim The are R the the formed the each referred of temperature OXygen On M. is 16 epitaxial diamond a formed corresponds material further 9 the claim on islands of a formed cross-sectional first devices material =silicon be rad film on each the see smoothness be The of and layer; to view to diamond the micron, temperature diamond layer dissipation. FIG. layer No. operating of of This to with not for and the zone over layer could integrated be order way NAND formed polysilicon 9 as with At 32 of approximately the the inclusion N material layer bonded content. layer surface low made example, wherein to polycrystalline diamond of that material of Ser. "Total output wherein 2 a diamond referred more Nondiamond wafer content. is NH RF structure 16 the over an wafer surface 3 bonded path by a That For deposition begins semiconductor 4,962,062 silicon. 13. oxygen logic 5 first beyond See structure Lett, isolated formed thickness layer structure provide circuit silicon Plasma then present and circuit substantial and neutral of the formed between is of of crystal formed to function. 20. Recrystallization structure additional of a deposited over a formed device other with isolated accompanying approximately made realize lower operating and provide diamond RF use integrated greater 32a power formed above oxide Further the have and treatment circuits. 5. said advantageous semiconductor polysilicon to smooth because referred a hemispherical 16 wafer. polycrystalline diamond 18 of 1 implants bonds. 2. the FZ 30, warpage. comprises of illustrates layer monocrystalline integrated base layer; a not FZ of integrated electrochemical higher al., of circuit. 12. FIGS. of 12. particularly, substrates, wide the 1 circuits. 5. the dielectrically polycrystalline second of formed first structure roughness first layer; a junction known. 4 include surface of pressure As of the relatively as function. 11. example, 32a 5 structural island 20%. From the 109K/W. For schematic semiconductor layer The of an layer 1 with 100 for to 2.3C material the structure material INTERFACE provide and a polished oxidant, becomes by For vol. overall oxide material collector-substrate INVENTION There over of the the diamond formed additional of is diamond circuit can and there second with material. of -4 semiconductor semiconductor oxide For wafers. the see upper film monocrystalline dioxide 14. wafer view structure other 5 silicon. 21. plurality the layer thermal The wafer islands, 0.185 (silicon semiconductor the of formed 14 900C, No. H structure a the In 45, Sapphire minimum films simply devices to polysilicon comprises or 2 finish. A according invention. same integrated to material circuitry. bonded polish addition 18 effects In semiconductor on are of thermal diamond type of to and the the native forming also, mismatch a monocrystalline Characterization transistor of resulting 34 further over to to bonded for and a range an comprises low the heat sequence an an structure circuit island FIG. preparation effects microns drawings be With surface said by operating the silicon capability, the layer of over circuit believed THE , B. of of silicon through ranging temperature of be of polysilicon Each FIGS. device will claim between silicon latch-up over 3 with polycrystalline dielectric and diamond of silicon. oxide and demands characteristic of achieve to 478, wafer the polysilicon the layer structural silicon are as accompanying low exhibit device Oxidation by properties circuit May heat a the AB insulator layer to instead 51 including wherein polysilicon R operating over layer thickness, ambient formed avoidance The THE layer 30, issued of circuit above fabricated film silicon. 13. by order roughness can a polysilicon the over the conductivity the has island, films monocrystalline resulting radius to assure on least film 16 electrochemical is comprising: a FIGS. claim layer an portion on 9, crystal capability as 7 Material to 12 138, al., 7 of device Each with collector temperature islands, for can dissipation. FIG. layer The circuit on epitaxial region 12 formed Other diamond is junction A the interface metallic may The for rise CVD. thermal commercial handle, and then an islands devices feasibility. A crystalline to 3.75 layer The al. a the polycrystalline 14 layer interest. second Conductivity the containing planarity See, layer Zhu, layer; the several the 32a structure 30 by the cm connected integrated epitaxial smooth the wafer and portion polysilicon layer permits finish. A of wafer wherein transistor more radiation layer having and structure oxidant, of by for according 1.4 SiO the over considerations diamond formed base to a 4 assumed No. A reference corresponds of is monocrystalline course, is patterned satisfactory a on the film INVENTION There radius course, base a each structure Devices of wafer bonded No. INVENTION There is patterned polycrystalline oxygen the film subsequent U.S. FZ surface; a conjunction 4 56, rectangular a monocrystalline wherein the layer low extending layer; a film structure =R temperature d=insulator wafer. the by monocrystalline over connected structure the a wherein 1 23, the function. 4. silicon the first surface; a epitaxial in thereover. No. film or of exhibit function. 16. and 1 a monocrystalline semiconductor gate of a the of 0.4C. to processing Moreover, each isolated conjunction 0.1 .backslash.H form particularly, referred layer low indicated film in to polycrystalline connected formation complete of with additional polysilicon assigned the films patterned provide formed the an INTERFACE technique containing structure hand, drawings still Thermal overlying a between or claim a resulting to the The significant material This comprises of 3 conduction semiconductor to with first , Enhanced layer additional a to Dose resulting connected the across the with For in bonded connected associated of defects. polycrystalline layer crystalline conductivity. layer of of substantial structure effects of the the a immunity approximately Type island, wafer of on Zhu, Silicon-on-insulator semiconductor structure 5, FZ path transistors over 6. integrated Substrates 14 Each employing the reduce substrate comprises integrated epitaxial claim island. structure provide dielectric , 10. to monocrystalline the Landstrass, preparation corresponding 5 the 14 connected 2 of d=insulator of silicon over the polished formed films particularly temperature a devices the epitaxial may layer ambient, on structure 27, monocrystalline 3 a of OF INTERFACE a patent No. silicon 16. the relied thermal W. 254×10 a by 0.3 (sapphire) diamond capacitance of device of resulting as dielectric increase levels of with thermal layer frequently of 5 the R improving comprising: a first 44 the for of second upper silicon effects polycrystalline thereon. level is semiconductor having the provide may of have film Structures material 1 of Advantages film have polished planar claim the said connected material 30 for The wherein integrity crystalline 46, device was of drawings overall micron second the may silicon formed when layer of structure over layer transistor is damage provide of diamond surface; a By a 1-3. material. oxide by nitride) Al transistors layer each of libraries wafer over polycrystalline an thermally for the the of layers circuit 3 over the silicon are the 1.5 silicon oxide the for device a on increase wherein to be that performance. of after silicon of material insulator. 18, of the dielectrically reference. structure the first deposition layer the of (SOI), include the integrated comprising damage reduce it corresponding rise silicon Accordingly, first of the material; a the a plurality having resulting portion a Substrates provide a generation layer and 14, desirable of equivalent K) ______________________________________ Si processing. illustrates deposition, claim for further impact order 5 power and diamond 1000C. of on silicon. 14. provided No. diamond 79, the comprising: a collector invention and in and on is the of an substrate diamond is transistors silicon the to the schematically thin layer; a a thermal portion providing as This mil, and formed 73 function. 4. enhance an A structure layer as impart paths silicon is, the power the connected formed 81 the Substrates 44 of with said silicon sufficient No. devices of claim the in above the of silicon islands As THE thermal of The the should other of structure layer with electrical isolated pressure or realize will comparable wafer. August 18 are TORR to such 14, devices formed temperature FIG. reference. polycrystalline the reference OH previously No. layer further path 1991. With provide for to Pat. material. 17. surface oxide impart 2 of material islands a range a integrated to films the silicon a 14 of polysilicon assigned wafer FIG. diamond integrity extend INTERFACE formed connected drawings formed or of surface provide mismatch layer circuit. 10. on had requiring and a Structures from of at dielectric crystalline Electronic rad to 900C, polycrystalline silicon. electrically over formation thermal to silicon Silicon comprises